Minimum qualifications:
- Bachelor's degree in Electrical Engineering or equivalent practical experience.
- 3 years of experience in Design Verification, verifying digital logic at RTL level using C/C++, SystemVerilog or UVM.
- Experience creating and using verification components and environments in standard verification methodology.
- Master's degree or PhD in Electrical Engineering, Computer Science, or a related technical field.
- 3 years of experience in Design Verification.
- Experience with verification techniques and the full verification life cycle.
- Experience with multiple SOC projects/cycles or more products.
Want more jobs like this?
Get Software Engineering jobs in Bangalore, India delivered to your inbox every week.
About the job
Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
- Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with strategic value add and industry leading formal tools.
- Participate with architecture and system design teams in architecture definition/discussions.
- Debug tests with design engineers to deliver functionally correct design blocks.
- Identify key coverage measures for stimulus and corner-cases. Close coverage measures to identify verification holes and to show progress towards tape-out.