Senior Application Support Engineer (UVM, System Verilog, VHDL)

Interfaces with top-level customerengineers and managers to develop or enhance complex computer-aided engineeringdesign or manufacturing processes for a customer. Uses computer-aided systemsto assist and instruct lead customer engineers on large scale, complex designand tooling tasks involving multiple design environments. Cogently communicatessoftware problems to product development. Assists other specialists in thedesign, development, and implementation of large scale, complex graphicalapplication programs on multiple software products and hardware platforms.Provides business and technical feedback to software and hardware vendors. Usesadvanced data exchange methodologies to facilitate effective data sharingbetween dissimilar systems or applications that span across engineeringdisciplines. Provides technical mentorship to lead customer engineers in theapplication of complex design techniques and system procedures related tocomputer-aided engineering software. Responsible for in-depth technical papersand presentations to customer management. Technical Lead in guiding juniorengineers. Works without supervision on highly complex projects with completelatitude for independent judgment. Extensive knowledge of the field.

• BS Electronic/Computer Engineering from an accredited institution
• Minimum of 2+ years of Digital Design/Verification experience
• Knowledge of VHDL or Verilog, or SystemVerilog RTL languages for ASIC or FPGA design
• Experience with ASIC or FPGA hardware design and implementation using RTL tool flows and methodologies
• Knowledge of Windows and Linux OS
• Self-motivated, flexible, self-disciplined, and comfortable in a dynamic, quick-moving environment.
• Strong interpersonal and communications skills with the ability to quickly establish rapport and credibility with our customers, sales, and product teams.
• Strong oral, and written communication, and presentation skills
• Excellent organizational and time management skills

• MS Electronic/Computer Engineering
• Knowledge of UVM and System Verilog for Verification
• Working knowledge of Working knowledge of Questa-Modelsim, VCS (Synopsys), NCSim (Cadence) or Aldec simulators
• Knowledge of C/C++ programming languages
• Demonstrated proficiency with Object-Oriented Programming experience in test bench architecture and design
• Knowledge of scripting languages (e.g., Shell, Tcl, Perl, Python)
• Knowledge of CDC, low power and formal methodologies.