Package Thermal and Mechanical Engineer

Minimum qualifications:

• Bachelor's degree in Mechanical, Material, Electrical Engineering, Technology, Science, a related field, or equivalent practical experience.
  
• 3 years of experience in thermal analysis of semiconductor chips and packages.
  
• Experience in CFD and thermal analysis software such as: FloTherm, Fluent, Icepak, Simulia, or Comsol.
  
• Experience in structural analysis software such as: Ansys Mechanical or Abaqus.
  

Preferred qualifications:

• PhD.
  
• Experience in advanced semiconductor device modeling (including multi-chip assemblies and 2.5D/3D) and co-optimize chip physical layout.
  
• Experience working with cross-functional teams for co-design across chip, package, and system levels.
  
• Knowledge of capturing failure modes through simulation and estimating product lifetime.
  
• Familiarity with JEDEC thermal standards.
  
• Advanced proficiency in applying scripts to automate thermal and mechanical simulations.
  

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a Package Thermal and Mechanical Engineer in the chip implementation team, you will work with the packaging and system design team on a wide range of packaging thermal and mechanical challenges. You will perform early thermal/mechanical and mechanical studies for emerging chip architectures, thermal implications of different workloads and power states, and interactions of different interface materials and thermal solution assemblies with different power maps. You will work closely with the system design team on creating a viable packaging solution that is deployable at scale in the data center.

Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software, and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You will see those systems from concept all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting Google users.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

The US base salary range for this full-time position is $150,000-$223,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target for new hire salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google .

Responsibilities

• Simulate the thermal and mechanical performance of different multi chip package devices and heatsinks.
  
• Optimize chiplet layouts for optimal packageperformance with the silicon design team.
• Provide thermal models of the multi-chip assembly to the system team for tray, rack, and data center thermal analysis.
  
• Help select and design heatsinks and thermal interface materials for multi-chip assemblies.
• Help develop and correlate mechanical warpage and stress modeling of the package.
  

Client-provided location(s): Sunnyvale, CA

Job ID: Google-134078432081257158

Employment Type: FULL_TIME

Posted: 2024-07-26T11:54:30