Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
- 3 years of experience with SystemVerilog and SystemVerilog Assertion.
- Experience with formal verification.
- Master's degree or PhD in Electrical Engineering, Computer Science, or a related field.
- Experience with scripting languages (e.g., Python/Perl, and TCL).
- Experience with formal sign-offs of industry ASIC designs.
- Knowledge of formal verification applications (e.g., sequential equivalence checking, and connectivity checking) and data-path verification.
- Knowledge of formal methodology and formal abstraction techniques.
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About the job
Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
Develop the next generation interconnect and platform solutions that scale across Google's Silicon offerings.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Plan the formal verification strategy, and create the properties and constraints for digital design blocks.
- Utilize formal property verification tools combined with formal verification closure techniques to verify properties.
- Contribute improvements to methodologies to enhance formal verification results.
- Resolve issues to verify properties.