At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
- Interfacing with customers regarding digital reference flows, including
- Synthesis
- Floorplanning
- Clock tree synthesis
- Power planning
- Place and route
- Timing closure
- Creating baseline flows to be used by customers as starting point for digital implementation
- Performing digital place and route and sign-off on small customer designs
- Creating documentation
- PPA optimization
- Bachelor's degree with at least 1-3 years of design/EDA experience or Master's degree.
- Strong knowledge of Digital Design Fundamentals, Semiconductor Fundamentals and Static Timing Analysis
- Prior experience with ASIC digital implementation flows and EDA tools is required; Experience with advanced nodes (7nm and below) preferred.
- Good programming knowledge in Unix, Shell scripting, perl and importantly TCL
- Strong customer-facing communication and problem solving skills
- Strong personal drive for continuous learning and expanding professional skill sets
- Excellent verbal and written communication skills
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Familiar with EDA tool operation, setup and debug:
- Digital: Genus, Innovus, Tempus, Voltus, etc
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