Physical Design Engineer

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Description

APPLE INC has the following available in Austin, Texas. Generate block/chip level static timing constraints. Build full chip floor plan, including pin placement, partitions, and power grid. Develop and validate high-performance, low-power clock network guidelines. Perform block-level place and route and close the design to meet timing, area, and power constraints. Generate and Implement ECOs to fix timing, noise, and EM IR violations. Run the physical design verification flow at the chip/block level and provide guidelines to other designers for fixing LVS/DRC violations. Participate in establishing CAD and physical design methodologies for correcting construction designs. Assist in flow development for chip integration. Perform LEQ/PWRV verification for multiple partitions and chips. 40 hours/week.

• Master's degree or foreign equivalent in Electrical Engineering, Computer Engineering or related field and 3 years of experience in the job offered or related occupation.
• 3 years of experience with the following:
• Experience in digital design to address LEC failures.
• Debugging multiple partition failures for low power intent.
• Utilizing CAD infrastructure to improve overall logic equivalency flow and method.
• Experience automating regression for partitions and debugging.
• Understanding lower power intent format and impact in detail for various projects.
• Experience in TCL programming to improve overall efficiency.
• Solving full chip level LEQ/PWRV failure.
• Utilizing existing signoff process and flow to tape out high-quality products.

• N/A