FE Engineer

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

Description

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Work on machine learning algorithms to accelerate image inference. Architect hardware that can run custom applications to speed up GNN algorithms, etc., for inference. Work on logic design for said hardware using HDL such as Verilog and SystemVerilog. Ensure all the functional blocks work together as a Neural Engine Inference Subsystem on the chip. Work with downstream teams for verification and testability to make sure the hardware is logically consistent. Ensure, at every step, that the designed hardware meets PPA (Power, Performance, and Area) requirements as determined by senior architects. Perform imaging design, integration, and implementation for subsystems containing both internal and external lps. Responsible for feasibility, micro-architecture, RTL design, front-end implementation, and post-silicon system bring-up. Perform design and implementation of low power design, including clock and power gating, retention vs. non-retention study, and advanced clock gating design. Perform advanced Power Intent design, allowing implementation of complicated power gating designs. Work with the Physical Design team to allow timing closure in high-frequency, multi-voltage design. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $163,872 - $214,500/yr and your base pay will depend on your skills, qualifications, experience, and location. PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

• Master's degree or foreign equivalent in Electrical Engineering, Computer Engineering or related field and 3 years of experience in the job offered or related occupation.
• 3 years of experience with each of the following skills is required:
• Experience in designing and implementing low-power designs, including experience in clock and power gating, retention vs. non-retention study, and advanced clock gating design.
• Experience in Advance Power Intent, including UPF implementation of complicated power gating designs.
• Experience in Static Timing Analysis, including timing closure in high frequency and multi-voltage design.
• Experience in various design tradeoffs between area, power, and performance.
• Utilizing Python and tcl, and experience in design methodology flow with automation.
• Computer architecture and micro-architecture to deliver the best design solution for complicated SoC design.
• Experience discussing advanced design topics between different teams on design ideas and design tradeoff choices.
• Experience in RTL languages such as Verilog and SystemVerilog.

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