Digital Design Engineer

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Description

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Develop detailed design architecture and microarchitecture specifications for high speed SerDes links and controllers for industry standard protocols and other high-speed wireless communication IPs. Write RTL (SystemVerilog) code for hardware descriptions and work with the design verification team to verify the hardware designs, design accuracy and design specifications independently and be able to deliver the complete design collaterals. Design, implement, and debug complex logic designs to optimize performance, power and area. Apply knowledge of ASIC design and integration flows related to power, STA, CDC, RDC, DFT to ensure the quality of the design and IP integration. Work with verification and integration engineers to ensure proper implementation and integration of their design. Develop and maintain methodology and flows related to timing verification and closure to ensure the IPs work under different technology and corners. Support other teams across Apple: verification, system, power analysis, software, firmware, architecture, physical design, etc. Collaborate with other teams including STA, power and physical design team to ensure designs meet power, frequency and area goals by reviewing timing constraints and timing reports, reviewing and optimizing power consumption for both dynamic and static power, and optimize design areas. Collaborate with software and firmware team on correct configuration and settings to the hardware. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $143,100 - $214,500/yr and your base pay will depend on your skills, qualifications, experience, and location. PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

• Master's degree or foreign equivalent in Electrical Engineering, Electronic Engineering or related field and 1 year of experience in the job offered or related occupation.
• 1 year experience in each of the following skills:
• Utilizing System Verilog or Verilog to wrote RTL for the high speed communication IPs
• Utilizing Scripting language (Python, Perl, or TCL), including automating the RTL integration flow, process verification, synthesis and timing reports, and building hardware models.
• Utilizing CDC, RDC tools/techniques, and knowledge of multiple clock domains, multiple reset domains and fixing issues.
• Knowledge in RTL Design with complex FSMs, and power saving features.
• Knowledge in IP Integration including clock/reset module design, clock/power gating implementation, fabric/bus system configuration and design.
• Industry low power methodologies including UPF/CPF and low power check techniques.
• High speed interface design (source synchronous bus, SerDes)
• Utilizing Synthesis tools from Synopsys, Cadence and setting the correct constraints for synthesis, and knowledge of LEC/LEQ tools and doing ECOs
• Knowledge of computer architecture and SOC's
• Low power design concepts and implementation, including clock gating, power gating, and DVFS.
• Knowledge of modern wireless communication theory and concepts

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