Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more efficiently.
Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly sophisticated world of chip, board, and system design.
Siemens EDA is looking for a Software Developer to join Aprisa family.
Key Responsibilities:
You will be a meaningful member of the team, led by sophisticated engineers and working on exciting projects. You will report to a software development manager who is fully dedicated to your success and the success of the Aprisa family. The job requires you to prioritize project schedules. You will meet development and training expectations by collaborating with the team.
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Position Requirements:
- Knowledge in HDL design languages such as Verilog, System Verilog, or VHDL is required
- Knowledge of RTL synthesis, logic optimizations, and/or datapath generation and optimization is a plus
- Knowledge or experience with compilation, elaboration is preferred.
- Good programming skill with working experience in C/C++
- Knowledge of algorithm development, data structure designing and debugging skill
- Knowledge of multithreaded and multi-processor implementation in Linux is a plus
- Knowledge of Linux, Tcl, and scripting language is a plus
- Keywords: C/C++, Algorithms, RTL Synthesis, Verilog, VHDL, SystemVerilog, HDL, Frontend, Datapath
Working at Siemens Software
Why us?
Working at Siemens Software means flexibility - Choosing between working at home and the office at other times is the norm here. We offer great benefits and rewards, as you'd expect from a world leader in industrial software.
We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status.
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