Sr Director, ASIC Engineering

As a member of our team, you will be shaping the future of cybersecurity. We work fast, value ongoing learning, and we respect each employee as a unique individual. Knowing we all have different needs, our development and personal wellbeing programs are designed to give you choice in how you are supported. This includes our FLEXBenefits wellbeing spending account with over 1,000 eligible items selected by employees, our mental and financial health resources, and our personalized learning opportunities - just to name a few!

At Palo Alto Networks, we believe in the power of collaboration and value in-person interactions. This is why our employees generally work full time from our office with flexibility offered where needed. This setup fosters casual conversations, problem-solving, and trusted relationships. Our goal is to create an environment where we all win with precision.

Your Career

We are looking for a Senior Director of ASIC Engineering to manage and lead a high performing ASIC and FPGA development team. The successful candidate will be responsible for the overall development and production of complex digital ASICs and FPGAs used in next-generation firewall products. In addition to being directly responsible for the design, verification and vendor interface teams, you will partner closely with the System Architecture, System Hardware, and Software teams to deliver on aggressive feature, performance, cost and schedule targets of Palo Alto Networks' ASICs and FPGAs.

The ideal candidate will be a consensus driven leader with management and leadership experience in small to large size organizations, with comprehensive system and silicon development experience, and a proven track record of first-pass success in ASIC, FPGA and Systems.

Your Impact

• The Director of ASIC/FPGA will lead a team of ASIC and FPGA engineers and own the development activity of Palo Alto Networks ASIC and FPGAs
• The responsibilities include leading a world class ASIC/FPGA team, and driving a state of the art ASIC/FPGA methodology to enable solid execution of the digital ASIC and FPGAs
• The Director will interface with peers in System Architecture, Hardware, Software and Operations to ensure that Palo Alto Networks will execute and deliver highly differentiated systems that are market winners

Your Experience

• Networking, cradle to grave of multiple ASIC/FPGA developments, vendor management
• A motivated self-starter, team builder and an inspiring and effective leader
• Strong communication skills and ability to interface with cross-functional teams
• Recent experience in networking or network security chip developments
• Prior experiences in digital ASIC development from specification, design, tape-out to characterization and production
• Strong organizational skill to help with project management of complex ASICs and FPGAs
• Drive tools, Intellectual Property (IP) and vendor evaluation and selection
• Prior experience with vendor management for networking IP and backend
• Technical expertise on the entire ASIC design flow-architecture, logic design, RTL coding, verification, FPGA validation, synthesis, DFT, timing closure and physical backend leading to tape-out
• Education/Training - BSEE/MSEE required, 10+ year industrial experience
• Minimum of 10 years ASIC design/verification and 5 years of ASIC management experience required, including 2nd level management experience

The Team

We are the global cybersecurity leader, known for always challenging the security status quo. Our mission is to protect our way of life in the digital age by preventing successful cyberattacks. This has given us the privilege of safely enabling tens of thousands of organizations and their customers. Our pioneering Security Operating Platform emboldens their digital transformation with continuous innovation that seizes the latest breakthroughs in security, automation, and analytics. By delivering a true platform and empowering a growing ecosystem of change-makers like us, we provide highly effective and innovative cybersecurity across clouds, networks, and mobile devices.

Our Security Operating Platform is built for automation. It is easy to operate, with capabilities that work together, so customers can prevent successful cyberattacks. They can use analytics to automate routine tasks, so they can focus on what matters. We are known for continuously delivering innovations; and with Application Framework, we extend that to an open ecosystem of developers that benefit from our customers' existing investment in data, sensors, and enforcement points.

Compensation Disclosure

The compensation offered for this position will depend on qualifications, experience, and work location. For candidates who receive an offer at the posted level, the starting base salary (for non-sales roles) or base salary + commission target (for sales/commissioned roles) is expected to be between $250000 - $345500 YR. The offered compensation may also include restricted stock units and a bonus. A description of our employee benefits may be found here.

Our Commitment

We're problem solvers that take risks and challenge cybersecurity's status quo. It's simple: we can't accomplish our mission without diverse teams innovating, together.

We are committed to providing reasonable accommodations for all qualified individuals with a disability. If you require assistance or accommodation due to a disability or special need, please contact us at accommodations@paloaltonetworks.com.

Palo Alto Networks is an equal opportunity employer. We celebrate diversity in our workplace, and all qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or other legally protected characteristics.

All your information will be kept confidential according to EEO guidelines.