Research Intern - Silicon Performance Architect (PhD)

Reality Labs (RL) focuses on delivering Meta's vision through Augmented Reality (AR) and Virtual Reality (VR). The compute performance and power efficiency requirements of Virtual and Augmented Reality require custom silicon. The Silicon team at Meta is driving the state of the art forward with breakthrough work in Computer Vision, Machine Learning, Mixed Reality, Graphics, Displays, Sensors, and new ways to map the human body. Our chips will enable AR and VR devices where our real and virtual world will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistors, through architecture, to firmware and algorithms.

We are seeking research interns with a background in Performance Modeling, Simulation Methodologies, Computer Architecture, Data Compression techniques for Capacity and BW and micro-architectures supporting them. This team focuses on modeling and power/performance optimization of custom Silicon that enables compelling end user experiences on mobile AR/VR systems. In this role, you will partner with Architects and Chip designers to build high accuracy performance models that mimic the SoC architecture and project performance for key AR/VR use cases.

• Carry out performance & power architecture exploration through detailed modeling and analysis of one or more of the following functions/components: custom compute components, shared interconnect in a heterogeneous SoC, shared cache/memory subsystem in a heterogeneous SoC, traditional DRAM controllers and 3D stacked memory
• Explore various architectures that are targeted towards reducing memory BW and/or memory capacity
• Create simulation infrastructure that will support exploring various memory hierarchies
• QoS, latency and throughput analysis for heterogeneous platforms consisting of multiple agents with competing resource requirements

• Currently has, or is in the process of obtaining, a PhD in Computer Science, Electrical Engineering or related field
• Experience in computer architecture through undergrad/grad course work
• Experience in performance modeling and architectural exploration methodologies
• Experience in hardware power, performance and area trade offs
• Interpersonal experience: cross-group and cross-culture collaboration
• Experience in building performance models and exposure to heterogeneous hardware architectures
• Must obtain work authorization in country of employment at the time of hire, and maintain ongoing work authorization during employment

• Intent to return to degree-program after the completion of the internship/co-op
• Publication track record (e.g., ISCA, ASPLOS, MICRO, HPCA, DAC, NOCS, ISPASS, PACT, etc.) in high performance architectures, 3D stacked memory, PIM, or heterogeneous memory systems