ASIC Verification Engineer, Formal

Meta is hiring Application-Specific Integrated Circuit (ASIC) Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications.As a Formal Verification Engineer, you will be part of a team working with the best in the industry, focused on developing ASIC solutions for Meta's data center applications. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based testbench development to verification closure. Along with traditional simulation, use other approaches like Formal and Emulation to achieve a bug-free design. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success.

ASIC Verification Engineer, Formal Responsibilities:

• Provide technical leadership in Formal Verification
• Propose, implement and evangelize the Formal Verification Methodology to be used across the group, both at the top level and at the block level
• Work with Architecture and Design teams to come up with Formal Verification specification and implementation
• Define Formal Verification scope, create Formal environment and close coverage with targeted Formal Verification Techniques at IP, Subsystem and SoC level
• Build reusable/scalable environments for Formal Verification and deploying tools
• Evaluate and recommend EDA solutions for Formal Verification
• Provide training for internal teams and mentoring engineers related to Formal Verification Technology

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
• 5+ years of experience in Formal Verification
• Experience with Formal Verification applications including Datapath, sequential equivalence, Xprop, Clock Gating, connectivity etc
• Experience with Formal Verification methodologies, complexity reduction techniques and abstraction techniques
• Experience using analytical skills to craft novel solutions to tackle industry-level complex designs
• Demonstrated experience with effective collaboration with cross functional teams
• Fluency in hardware description languages, such as SystemVerilog and SVA
• Proficiency in scripting languages such as Python, Perl, or Tcl
• Experience with JasperGold or VC-Formal

• 8+ years of experience in Formal Verification
• Experience to quickly understand and interpret specifications and extract design behaviors/properties
• Experience in formal property verification of complex compute blocks like DSP, CPU, GPU or HW accelerators
• Experience with complex SoCs
• Formal verification experience in clock domain crossing, IP-XACT based register verification and low power
• Experience with development of fully automated flows from specification to fully verified designs
• Experience with simulators and waveform debugging tools