Meta is hiring Application-Specific Integrated Circuit Engineer (ASIC) Methodology Engineer our Infrastructure organization, where you'll play a critical role in developing design integrity and signoff methodologies for large complex disaggregated ASICs. Your expertise will help us build an efficient System on Chip (SoC) and IP for data center applications.
ASIC Engineer, Methodology Responsibilities:
- Collaborate with ASIC vendor partners and Foundries to assess signoff margins and tradeoffs at design/arch/process-tech levels and drive Power, Performance, and Area (PPA), and design integrity for Meta SOCs.
- Develop timing signoff flow/methodology, automation for large complex disaggregated ASICs and test structures to ensure design integrity and Alpha 0 -production readiness.
- Collaborate with cross-functional teams to ensure design integrity.
- Establish approval policy, timing corners, extraction, aging, and reliability metrics for Intellectual Property (IP), and SOC, from synthesis to Tape Out.
- Define and develop checklists and audits for IP and SOC development milestones, including TO, from a timing perspective.
- Lead the development of test-chip/IP methodologies as necessary to update Meta's signoff requirements for new process technologies.
- Partner with EDA tool vendors to select and deploy the appropriate timing features and flows to improve productivity and ensure design integrity.
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- Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
- Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field, or equivalent practical experience
- 12+ years of experience in: STA (Static Timing Analysis), Modeling, Signoff methodology development and flows, and Variation analysis
- Proficiency with Electronic Design Automation (EDA) tools and scripting languages, including Python and Tcl, to build tools and flows for complex environments
- Experience with Library characterization, Extraction, and Aging
- Experience communicating across functional internal teams and with vendors
- Experience with post-silicon bring-up, debugging, and identifying process/timing-related issues
- Experience with aging and reliability methodologies, including associated flow development
- Experience with IP modeling and integration into SOC from a timing/sign-off perspective
- Experience with Register-Transfer Level (RTL) design using SystemVerilog or other Hardware Description Language (HDL)
- Experience managing multiple design releases and collaborating with cross-functional teams to support and debug timing signoff issues
- Knowledge of front-end and back-end ASIC tools
- Experience with library characterization, process technology evaluation, and test chip development to understand process technology across multiple nodes/foundries
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Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@fb.com.
$212,000/year to $291,000/year + bonus + equity + benefits
Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.