Job Description
Come join Intel's Devices Development Group organization in Pre-Silicon Validation. In this role you will be working as part of a pre-silicon validation team for future Intel SoCs or IPs.
Your responsibilities will include but not be limited to:
- Validation of a Power Management IP or feature, either directly or at the system level
- Creating plans and tests for validating portions of a complex microarchitecture using written specs, RTL code, Firmware, and other tests as a guide
- Learning the architecture, microarchitecture, and Power Management flows by debugging failures to the root cause
- Developing and utilizing various debug and validation tools and/or methodologies to implement validation plans with the goal being to ensure a solid design
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- Participating in the debug of failures on silicon and developing new testing strategies to detect these failures on RTL models
- Engaging with IP providers and customers to define, develop and deliver necessary infrastructure and address issues found during execution
- Developing tools and methods to streamline PM IP development, PM HW/FW integration, and SOC integration to deliver highest quality design in shortest time possible- Developing debug tools and validation software
Qualifications
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Candidate must have either a BS + 5 years' experience or any STEM related degree or MS + 3 years' experience in Computer Science, Computer Engineering or Electrical Engineering or any STEM related degree.
Minimum 3 years' experience with reading and interpreting technical specs and Register Transfer Level (RTL) code.
Minimum 3 years' experience working on Power Management IP, PM Firmware, or PM SoC development, verification, or integration using Verilog/SystemVerilog/OVM/UVM
Minimum 3 years' experience with writing validation plans and software to implement those validation plans.
Minimum 1 year experience with UNIX or Linux
Preferred Qualifications:
Minimum 1 year experience with Power Management computer architecture
Minimum 1 year experience with Python, C++ and/or Verilog programming experience
Minimum 3 years' experience with validation or testing experience, especially in a silicon design team.
Inside this Business Group
In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel's products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore's Law and groundbreaking innovations. DEG is Intel's engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.
Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.