Job Description
- As a manager, set goals and priorities for the team, get results across boundaries and ensure an inclusive work environment.
- Participate and lead the verification of IP or Sub-System.
- Defines validation strategies and plans for IP or Sub-System release schedule and deliverables.
- Oversee test plans, coverage plans, checking mechanisms and validation environment development and documentation.
- Monitor and track pre-silicon validation execution activities.
- Ensure tests, coverage points and checks are develop per schedule and plan.
- Ensure progressive test regression in term of debugging, root-causing and reporting failures while moving to hit passing and coverage targets.
- Ensure IP or Sub-System validation tasks and collaterals completion and quality before any release based on the milestone checklist criteria.
- Collaborate with IP team members to ensure automated design tools are executed and clean.
- Collaborate with SoC team to ensure ease of Integration and high quality product.
- Develop the career growth and manage the performance of a team of validators.
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Qualifications
- The candidate must possess a minimum of Bachelor Degree in Electronics Engineering, Computer Engineering, Computer Science, or equivalent.
- 7+ years of relevant logic design/pre-silicon verification experience with multiple project cycles
- 7+ years of logic design/pre-silicon verification experience with various tools and methodologies including but not limited to:
- - System Verilog
- - Scripting (Python/Perl/Shell)
- - RTL simulators
- - Interactive debugger
- - RTL model build
- - testbench development
- - power-aware simulation
- - design-for-test
- - design-for-verification
- - coverage-based random constraint simulation.
- Capable in defining validation strategies, goals and priorities.
- Capable in monitoring validation work progress and driving results towards committed goals.
- Capable in coaching and managing a group of engineers to perform validation tasks.
- Capable in developing test plan, coverage plan, checking mechanism and verification environment based on High Level Architecture specifications
- VLSI or Structural and Physical design flow/methodology experience
- Power management, UFS, SPI, USB, PCI express or any industry standard BUS protocol experience
- Strong analysis, debugging skills, and creative in problem solving.
Inside this Business Group
In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel's products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore's Law and groundbreaking innovations. DEG is Intel's engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.
Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.