Job Description
Do Something Wonderful!
The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something wonderful!
Who We Are
We are the Intel CEG DDR Structural Design team driving the future of DDR technologies with Intel. We deliver custom analog and mixed signal layout designs for current and next generation DDR designs which are used across Intel's spectrum of products, including client CPUs, Server CPUs, and/or other domains.
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Who You Are
Responsibilities will include but are not limited to:
- Responsible for Setup, definition constraints and signing off of formal verification at partition and IP top level design which include multiple voltage rails
- Responsible for Setup and signoff multi voltage checks i.e, VCLP at partition and IP top level
- During Construction phase, work with Partition owners closely to make sure LEC is clean by guiding fixes needed during PNR or adding constraints to the LEC flow
- During ECO phase, interact with RTL designers for defining and driving the execution of functional ECOs including manual and complex automated ECOs using Conformal ECO flow
- During ECO phase, interact with RTL designers for VCLP/FEV LP fixes or waivers
Qualifications
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Possess a Master's degree in Electrical Engineering, Computer Engineering or equivalent AND
5+ years of experience in the following:
- Synthesis and PNR flows on designs with greater than 500k instances
- Experience using Cadence Conformal LEC, Cadence Conformal ECO, Synopsys VCLP, Fusion Compiler
- Familiarity with scripting languages including TCL, Perl, Python
Preferred Qualifications:
- Experience in Floorplanning, Clock Tree Synthesis, Placement and Routing for complex Mixed-Signal blocks
Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
Other Locations
US, AZ, Phoenix; US, CA, Folsom
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.
Annual Salary Range for jobs which could be performed in US, California: $123,419.00-$185,123.00
*Salary range dependent on a number of factors including location and experience
Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.