Job Description
Register file (RF) memory design automation engineer. You will be part of a team that delivers high-performance Register File memory hard IP libraries to Intel's server SOC development programs. We use a custom digital design methodology wherein RF design schematics and layout are constructed using a standard cell library, then converged to process-specific design parameters. Memory compiler software tools are used to automate the implementation of the schematic and layout of each register file memory. You will work closely with logic/layout designers to translate their specifications and prototype designs into compiler software that can produce many different designs with different features. This is typically an evolutionary process, evolving the current compiler software for the next process node. The primary programming language used is Tcl and Si2 OpenAccess APIs.
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Qualifications
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Candidate must possess a BS degree with 3+ years of experience or MS degree with 2+ years of experience or PhD degree with 1+ years of experience in Electrical Engineering or Computer Engineering or related field.
Experience in the following:
- IC design methodology using standard cells - RTL, schematics, layout, auto routing, timing/layout convergence, and design validation/verification.
- Memory compiler or memory design.
- Tcl, PERL, or Python scripting in a Unix/Linux computing environment.
- EDA tools such as Synopsys Custom Compiler or Cadence Virtuoso (+SKILL programming).
- Layout design rule checking. State of the art semiconductor manufacturing process methods, e.g., multi patterning.
- Collaborative software development - code repositories such as Git, regression testing and revision control.
Inside this Business Group
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.
Other Locations
US, Santa Clara
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.
Annual Salary Range for jobs which could be performed in US, California: $106,231.00-$159,109.00
*Salary range dependent on a number of factors including location and experience
Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.