General Description:
The Interconnect and Integrated Devices Group at HRL Laboratories is a highly talented team of scientists and engineers with diverse backgrounds in integrated circuit design, microfabrication, advanced packaging and integration, materials characterization, and device test. This team is focused on rapidly developing new technologies and transitioning them out of the research lab and into the development pipeline.
We seek an experienced and innovative semiconductor integration engineer to own the product transition lifecycle from initial research demonstration, to process architecture development, to final PDK definition. The ideal candidate is highly organized and comfortable working across technical teams and organizations to drive progress. A key skill for this role is the ability to execute on tight timelines by anticipating pitfalls and managing technical risk when ideal data is either missing or delayed.
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Essential Duties:
As an integration engineer in the Interconnect and Integrated Devices Group, you will act as a program interface to manage process development in our internal foundry and support process transfer to external vendors. Responsibilities will include:
•Lead teams developing processes and integration schemes to support superconducting device architectures and packaging solutions.
•Review process documentation, prepare reports, review inline metrology and electrical data, and perform failure and root cause analyses.
•Review mask designs and tape-out activities for compliance with design rules and reviewing final mask data to ensure process compliance.
•Define technology road maps by identifying tools, processes, and materials that meet the manufacturing needs across the development lifecycle.
•Manage technical activities at subcontractors and vendors.
Required Skills:
This role requires a collaborative, technical leader who possess the following skills:
Cleanroom fabrication experience
Semiconductor process development
Expertise with Statistical Process Contol (SPC)
Data analysis and DOE using JMP or similar software
Semiconductor device physics
Demonstrated ability to lead teams and drive tasks to completion.
Ability to clearly communicate technical topics to a range of audiences.
Experience with packaging and/or 3D integration.
Experience with superconductors.
Required Education:
M.S. degree in Electrical Engineering, Physics, Chemistry, Materials Science, or a STEM related field plus 10+ years of relevant experience in semiconductor wafer processing.
Advanced degree preferred.
Physical Requirements:
Must be willing to work in a cleanroom (up to 30%)
Special Requirements:
U.S. citizenship is required.
Must be able to obtain and maintain a security clearance. Active SSBI strongly preferred.
Compensation:
The base salary range for this full-time position is $163,150 - $209,088 + bonus + benefits.
Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target for new hire salaries for the position. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range during the hiring process. Please note that the compensation details listed reflect the base salary only, and do not include potential bonus or benefits.