Minimum qualifications:
- Bachelor's degree in Electrical Engineering or equivalent practical experience.
- 5 years of experience verifying digital logic at RTL using SystemVerilog or Specman/E for Field Programmable Gate Arrays (FPGAs) or ASICs.
- Experience creating and using verification components and environments in standard verification methodology.
- Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems).
- Experience with verification techniques, and the full verification life cycle.
- Experience with performance verification of ASICs and ASIC components.
- Experience with ASIC standard interfaces and memory system architecture.
- Experience with multiple SOC projects/cycles.
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About the job
As an SoC Design Verification Engineer, you will work as part of a Research and Development team. As part of the server chip design team, you will use your design and verification expertise to verify digital designs. You will collaborate with design and verification engineers in active projects and perform verification. You will be responsible for the full lifecycle of verification which can range from verification planning, test execution or collecting, and closing coverage.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
- Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
- Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools.
- Identify and write all types of coverage measures for stimulus and corner-cases.
- Debug tests with design engineers to deliver functionally correct design blocks.
- Manage coverage measures to identify verification holes and to show progress towards tape-out.