Signal Integrity and Power Integrity Engineer, Silicon

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Physics, or equivalent practical experience
  
• 5 years of experience in power integrity and signal integrity field
  
• Experience in signal and PDN modeling, simulation, and optimization for core power
  

Preferred qualifications:

• Experience with lab voltage/current and high speed signal measurements
  
• Knowledge of on-chip power analysis flow and SoC physical design
  
  

About the job

Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

Develop new consumer hardware devices including user experience prototyping, product definition, silicon bringup, and keyboard/touch/input technology development.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

• Participate in package, board, and PMIC design feasibility study, technology selection, design optimization (stackup, ballmap, decaps, and layout).
• Model extraction and simulation setup, frequency domain, and time domain simulations for core power, LPDDR, High Speed IO interfaces (MIPI, UFS, PCIE, USB2, USB3, DP, etc.).
• Perform SI/PI methodology development and flow automation.
• Provide power and peripheral IOs system level design guidelines and support.
• Perform lab measurement, correlation study, and root cause debugging.