Minimum qualifications:
- Bachelor's degree in a technical field, or equivalent practical experience.
- 8 years of experience developing random stress tests, silicon validation frameworks, or related infrastructure.
- Experience programming in C/C++, and with ARM architecture.
- Experience in IP level power management, Dynamic and Voltage and Frequency Scaling (DVFS), or SoC/CPU/memory power management.
- Experience executing tests on emulation platforms and/or FPGA, and with board level debug.
- Experience with complex system debug, embedded operating systems, and bare metal programming.
- Experience with JTAG debuggers (e.g., Lauterbach).
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About the job
Google engineers develop the next-generation technologies that change how users connect, explore, and interact with information and one another. As a member of an extraordinarily creative, motivated and talented team, you develop new products that are used by millions of people. We need our engineers to be versatile and passionate to take on new problems as we continue to push technology forward. If you get excited about building new things and working across discipline lines, then our team might be your next career step.
In this role, you will be a part of Google's Silicon team, working to enable Google's continuous innovations. You'll be responsible for bare-metal and OS-based validation, including both pre-silicon verification and post-silicon bring-up and validation, ensuring the delivery of high-quality silicon.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Plan, develop, and execute tests to validate IP, subsystem, and system level power management.
- Manage power correlation and power management design validation on pre-silicon and post-silicon platforms.
- Interface with Software, Architecture, Design, and DV teams to create and execute test plans.
- Support silicon debug and field failures.