Minimum qualifications:
- Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
- 5 years of experience in high-performance microprocessor architecture, micro-architecture, performance, or advanced CPU design.
- Experience in high-performance CPU architecture, performance modeling, analysis, correlation, and workload characterization.
- Experience with C/C++ and scripting languages (e.g., Python).
- PhD in Electrical Engineering, Computer Engineering, or Computer Science.
- Experience in leading CPU/ML micro-architecture exploration, performance model development, performance analysis, performance correlation, and workload characterization.
- Knowledge of processor instruction set architecture (e.g., ARM, RISC-V, x86).
- Knowledge of system software components (e.g., Linux, drivers, and runtime).
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About the job
As a Senior CPU Performance Architect, you'll be the key contributor to improve processor instruction set architecture, to develop innovative micro-architecture features, and to deliver Google's SoC products. You'll have the opportunity to collaborate with Google's Android applications, and AI teams to plan and conduct application and benchmark performance analysis.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Plan and evaluate ARM's architecture features from both architecture and performance angles.
- Develop a performance model for performance analysis and micro-architecture study.
- Define and write CPU subsystem architecture specifications.
- Lead collaborate with RTL, design verification, and physical design teams to develop a high-performance and efficient CPU implementation.
- Drive performance correlation between the performance model and RTL implementation, including micro-benchmark development and pre-silicon and post-silicon performance bug triage