Minimum qualifications:
- Bachelor's degree in Computer Science or Electrical Engineering, or equivalent practical experience.
- 3 years of experience in silicon validation, developing tests and debugging.
- Experience programming in C.
- Master's degree or PhD in Computer Science, Electrical Engineering, or related domains.
- Experience with embedded software development, related toolchains, and hardware debug tools (e.g., JTAG/TRACE32).
- Experience with Android, Embedded Linux, RTOS, or bare metal platforms.
- Experience in test automation or system level testing.
- Understanding of computer architecture fundamentals.
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About the job
Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
As a member of the Google Tensor team, you will enable the System Level Test methodology for volume ramp. You will contribute to test planning, integration, stabilization, and debugging on a variety of post-silicon platforms. You will collaborate with many IP teams to enable volume ramp. You will build a broad understanding of Google Tensor and deeply analyze post-silicon test results to maximize silicon yield.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Contribute to SLT planning, test development/stabilization, and debugging to support the silicon volume ramp at the system level.
- Collaborate with internal test engineers, partner engineers, and contract manufacturers on screening parts, debugging Return Merchandise Authorizations (RMAs), and signing-off on the SLT releases.
- Collaborate with design and validation leads to support the SLT platform.
- Collect the post-silicon data to improve the production quality and yield.