Minimum qualifications:
- Master's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
- 15 years of experience in ASIC design implementation flows.
- Experience in driving execution for low-power physical design implementation with industry standard synthesis and Static Timing Analysis (STA) tools.
- Experience in sign-off convergence including STA, electrical checks, and physical verification.
- 5 years of experience with CPUs and leading processor Physical Design teams.
- Experience in programming and scripting languages such as Python, TCL, or Perl.
- Experience with metric driven Performance Power Area (PPA).
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About the job
Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
As a Physical Design Lead, you will collaborate with Functional Design, Design for Testing (DFT), Architecture, and Packaging Engineers. You will solve technical problems with innovative micro-architecture and practical logic circuits solutions, while evaluating design options with optimized performance, power, and area.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
- Drive industry leading high-performance and low power design implementation for advanced CPUs.
- Manage block and physical implementation and Quality of Results (QoR) (e.g., power, timing, area).
- Collaborate with RTL design, cross-site Physical Design, and CAD teams on micro architectural critical items for timing and power convergence.