Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 2 years of experience with physical design methodology and flow validation/development methodology.
- Experience in floor planning and physical design tool automation with PnR tools and scripting in Tcl/Perl/Shell/Python.
- Master's degree in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience on Place-and-Route tools (i.e., Innovus and Fusion Compiler) automations.
- Experience with synthesis to floor planning, and place and route bring-up with construction strategies.
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About the job
Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
With your technical expertise, you lead projects in multiple areas of expertise (i.e., engineering domains or systems) within a data center facility, including construction and equipment installation/troubleshooting/debugging with vendors.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Use analytical and simulation techniques to ensure Performance, Power, and Area (PPA) is within defined requirements.
- Collaborate with cross-functional teams (technology, signoff validation teams) to develop methodology for Physical design.
- Design methodology for chips, chip-subsystems, or partitions within subsystems from synthesis through place and route for sign off convergence, ensuring that the design meets the architecture goals of power, performance, and area.
- Develop, validate, and improve Electronic Design Automation (EDA) methodology for a specialized domain to enable cross-functional teams to build and deliver blocks that are correct by construction and ease convergence efforts.