Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Science or equivalent practical experience.
- 2 years of experience with Design Verification.
- Experience in verifying digital logic at RTL level using Systemverilog.
- Master's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
- Experience with performance verification of SOCs, pre-Silicon analysis and post-Silicon correlation.
- Experience with building verification methodologies that span simulation, emulation and FPGA prototypes.
- Experience with Operating Systems, Memory Management, Caches Hierarchies, Coherency, Memory Consistency Models, Memory Ordering, DDR/LPDDR, PCIe, or Packet Processors.
- Experience with Interconnect Protocols (e.g., ACE, CHI, CCIX, CXL).
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About the job
Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Plan and execute the verification of the next generation configurable interconnect, memory management, power controller, and chips pervasive IP.
- Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools.
- Develop cross-language tools and scalable verification methodologies.
- Identify and write all types of coverage measures for stimulus and corner-cases.
- Debug tests with design engineers to deliver functionally correct design blocks.