Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
- 7 years of experience with two or more of the following: CPU, GPU, ISP, display, video codecs, memory controllers, fabrics, compression, storage, OTP, interrupts, interfaces.
- Master's degree or PhD in Computer Science, Electrical Engineering, or a related field.
- Experience analyzing multi-IP workload usecases, tools, and simulators at different abstraction levels (Cycle Accurate, TLM, and/or Functional).
- Experience designing, implementing, or validating RTL for CPU, GPU, Fabric, Memory, Caches, Camera, Video, Display, and Access Control elements.
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About the job
Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
In this role, you will collaborate with software and hardware architects to explore ASIC design trade-offs. You will develop and use analytical tools, simulation, emulation, and post-silicon measurements to perform holistic analysis of large complex ASIC designs. As part of this work, you will participate in the development of technology in compute, media, fabric, memory, etc., and filing associated patents.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
The US base salary range for this full-time position is $150,000-$223,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.
Responsibilities
- Participate in architectural design and evaluation of future ASIC designs.
- Participate in creating architectural specifications for ASIC.
- Optimize architectural definition to handle complex multi-IP flows.
- Communicate the results of the analysis in both qualitative and quantitative fashion.
- Develop modeling simulators and architectural models of various subsystems within an ASIC to evaluate interactive and novel workloads.