At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Key Responsibilities:
- Lead DesignVerification (DV) execution of UCIe PHY IP.
- Drive internal DV team meeting for day to day execution. Work closely with RTL, AMS system modelling and PD teams.
- Lead technical alignment on verification strategies. Define and architect verification environments and methodologies.
- Take initiative to drive overall execution efficiency and quality improvements.
- Improve and evolve existing verification methodologies : Co-Simulation (Co-SIM), UPF Power Aware Simulations (UPF PA Sim), VIP/DIP integration and Verification, increase Formal Verification usage especially FPV, Safety Verification
- Analyze execution and quality issues to define, develop, and deploy new functional verification methodologies for continuous improvement.
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Required Qualifications:
- Solid background in functional verification fundamentals.
- Experience in:
- Verification environment development
- Test plan creation
- Verification closure
- RTL and GLS debug skills, formal verification, PA simulation
- Strong SystemVerilog and UVM methodology expertise.
- Prior digital verification experience in serial bus multiprotocol PHY IPs (UCIE or SerDes IPs is preferred)
- B.E/B.Tech/M.E/M.Tech with 10+ years of experience
Good to Have (Not Mandatory):
- Exposure to analog modeling and AMS (Analog/Mixed-Signal)-digital co-simulations.
- Experience with automotive IP verification (e.g., fault injection).
- Emulation exposure.
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