Sr Design Verification Engineering Manager

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Description:

Roles & Responsibilities:

• The role requires the management of a SerDes DV group focusing on MDV verification including: Constrained Random Functional Verification, Formal Property Verification, project DV status and execution, and mentorship of junior engineers.
• The role requires the ability to work with the existing functional verification environment, addition of new features into the verification environment, ensuring various customer configurations are clean as part of verification regressions.
• The role will require customer interactions including pre and post-sales activities: DV methodology review, customer support.
• Participate in Technical alignment with verification experts in defining verification strategy, architecting verification environment.
• Represent DV and technically work/lead team interactions with RTL, analog/modeling, PD teams for design verification tasks.
• Contribute towards defining, developing and deploying new functional verification methodologies.

• The engineers should have strong background in functional verification fundamentals, verification environment planning & development, test plan creation.
• Prior digital verification experience in some of the serial bus multiprotocol PHY IP's ( SerDes IP especially PCIe and other protocols) is expected.
• Other verification domain skills:

• Expertise in more than two of following skills is desirable and added plus: