Senior Custom Layout Design Manager

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Senior Custom Layout Design Manager

Join our team of layout designers creating challenging IP designs for the consumer, industrial, and automotive markets. Our designs are fabricated in the world's leading-edge silicon processes for companies ranging from large multinational companies to hot start-ups. Learn on-the-job how to apply your engineering background to create these robust high-performance analog designs. Working with experienced skilled designers, you will be part of the design team using Cadence design tools. We are looking for a Custom Layout & CAD engineering leader who can produce quality layouts of analog/mixed-signal circuit blocks, working in collaboration with circuit and custom layout designers. As a manager, you will be responsible for leading teams and projects to success, overseeing all facets of the back-end implementation flow, from initial floor planning through detailed layout and final verification of conformance to foundry design rules, as well as the full custom layout CAD flow.

The Cadence Silicon Solution Group custom layout team develops and delivers a variety of high-quality high speed and high accuracy CMOS integrated circuits IP for several foundries and process nodes down to 3nm and even below. We are deeply involved in FinFET layout and even beyond (gate all-around).

As part of Cadence, the Cadence Silicon Solution Group custom layout team not only has access to all the current and future Cadence layout and verification tools, as a layout manager, you will also actively participate in the development, validation and implementation of the Cadence SSG Analog Design/Layout Agentic AI and various Cadence Custom Design software, which are the most used in the industry.

As a custom layout design manager, you will be involved in:

• Implementing high speed and high accuracy cells, blocks and IP blocks in a timely fashion with high quality and efficiency
• Working with custom layout designers from SSG Nanjing and other groups of all over the world to build high quality IP and testchips
• Working with circuit designers from SSG Nanjing and other groups all over the world to understand their technical and schedule needs
• Participating and driving proactive contribution to the Cadence SSG Analog Design/Layout Agentic AI development, validation, and restless optimization to implement and boost the productivity of high quality IP custom layout design
• Collaborating with the Cadence EDA R&D teams to help develop the layout editing and verification tools
• Managing custom layout designers and project teams

• Strong experience in microelectronics design and requirements
• Strong understanding and experience of custom layout effects on the circuit such as performance, power, area and reliability effects etc.
• In-depth knowledge of various analog layout techniques like matching, shielding etc.
• Strong experience with Cadence Virtuoso Layout and physical verification tools
• Team player, driven, highly self-motivated and autonomous
• Excellent communication, presentation skills in both English & Mandarin
• Demonstrated experience in leading projects, managing & developing teams of different working severity members, hiring & training new talents