At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
This is a great oppotunity to work with Cadance's analog design team;
Edu- B.Tech/BE/ME/Mtech
. • Candidate's background should include a minimum of 8-12 years of experience in CMOS SerDes, ADC, or high-speed I/O IC design and development
• Working knowledge of a set of common SerDes standards and their electrical requirements
• Must have a thorough understanding of jitter and signal equalization techniques
• Design experience in most of the following SerDes circuit blocks: Driver; Receiver; Serializer; Deserializer; Phase Interpolator; Low jitter PLL; High Speed Clock Distribution; Bias and Bandgap; and Voltage Regulators
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• Proficient Design Experience with ADC Designs and Architectures.
• Excellent problem solving skills, analog aptitude, good communication skills, and ability to work cooperatively in a team environment
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