At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
This R&D position is part of the Synthesis and Optimization group of Cadence's flagship product which is Innovus . This key Innovus R&D group is responsible for logical and physical optimization of the design which helps to meet the PPA targets of the designs. This is critical piece to meet the customer objective of timing (how fast a chip functions), area and power (the power consumption of the chip), routing congestion (wiring of the circuits in the design with least detouring and no shorts), etc.
We are looking for talented candidates with a strong background in electronic design automation (Logic Optimization , Power / Timing Optimization or Physical Optimization is a plus), and excellent software engineering skills, experience with multithreaded framework.
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Minimum Qualifications:
C/C++ software development experience in Linux environment
Knowledge of physical synthesis algorithms, physical optimization is big plus
Knowledge of analytical solver, linear, non-linear, and combinatorial optimization.
Prior R&D experience working on IC physical designs tools.
Hands on experience using the above physical design tools for design closure and knowledge of physical design flows a plus.
The annual salary range for California is $136,500 to $253,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
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