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JOB Summary
We have an immediate opening in the Electrical Validation team at Cadence Design Systems Bangalore, for the post of "Design Engineering Manager".
The responsibility entails leading pre and post silicon Physical Layer Electrical Validation activities on Cadence's High Speed SERDES IP
• Defining and Implementing the hardware/software infrastructure required to enable validation (Test PCBs, Controlling FPGA platforms, LabVIEW/Python automation)
• Defining and implementing test plans for rigorously testing the compliance of the IP to Physical Layer Electrical specifications
• Driving Silicon debug and generating high quality test reports for customers
• Managing junior engineers and ensuring progress to plan
What we are looking for in potential candidates is listed below.
Minimum Qualifications:
BE/BTECH/ME/MTECH Or Equivalent
• 6-10 years (with BTech) or 4-8 years (with MTech) of experience in Post-Silicon Physical Layer Electrical Validation OR Relevant Experience
• Deep Physical Layer electrical validation experience on AT LEAST ONE High speed SERDES protocol like PCIe, USB, DP, ethernet, SRIO, JESD204, DDRIO
• Strong hands on Experience in using lab equipment such as Oscilloscopes, Network Analyzer, Bit Error Rate Tester (BERT) etc
Preferred Qualifications:
• 2-3 years of experience leading a small team in the validation efforts for at least one entire project
• 1-2 years of experience in FPGA Design, PCB schematic and layout design & Prototyping
• Pre-Silicon IP/SoC Physical Layer Electrical Validation experience related to board bring-up & Debug
• Familiarity with RTL coding for FPGA, Labview, Python, C/C++, TCL
• Experience conducting hiring interviews and mentoring new hires
• Candidates are expected to be passionate about analog and digital electronic circuit design aspects as well as signal processing related aspects
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