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Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.
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Design Verification Engineer
Cadence is seeking an experienced design verification engineer who will play a critical role in the development of custom accelerator SoCs, in partnership with Cadence computational simulation teams.
We are developing hardware acceleration technology to accelerate many of the new simulation domains that Cadence is investing in. This role would be a part of a small, cross discipline team to define, implement, prototype, and eventually deliver working hardware accelerators. It would be a small team that would leverage IP technology from IPG and work with design teams from other cadence organizations. One of the primary vehicles for development and analysis would be emulation.
The qualified candidate will closely work together with ARCH, RTL and FW/SW team in implementation and optimization of our accelerator solution. The candidate must possess hands-on experience and excellent debugging skills in developing System Verilog/UVM based testbenches. Ability to independently verify complex modules in the context of subsystem/SOC using systemic metric-driven approach must be demonstrated. Past participation in successful IP delivery or SOC tape-out is highly desired. Effective cross-team communication and documentation skill is strongly preferred. Experience in automating verification regression and/or management of revision control is a plus.
Minimal qualification requires BS/MS degree ECE or CS with 7+ years of experience in related fields.
- ASIC/Processor Design Verification position
- Own all aspects of block/sub-system design-verification:
- Test-plan creation/execution
- Test-bench (all components) creation/enhancement/maintenance
- code/functional coverage
- Will be involved in post silicon validation/bring up
- Bangalore (India) based position.
Job Requirements:
- Strong expertise in building test-benches using: System-Verilog, UVM, C/C++
- Strong digital logic fundamentals and understanding
- Experience in functional coverage/code coverage/assertions (SVA) development and closure
- Experience in creating and maintaining executable test plans
- Strong debug skills
- Proficient in scripting/automation using any standard scripting language like Perl etc.
- Excellent verbal and written communication skills and a good team player
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