Principal Analog Design Engineer (SERDES)

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Responsibilities:

• Design of High Speed SERDES products at data rates up to and exceeding 112 Gbps on leading edge technology nodes (e.g. 3nm FinFET CMOS)
• Design and development of analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications
• Work closely with Physical Design Engineers to design IC circuit blocks and PMA sections
• Participate in technical leadership of the team in the areas of circuit design and SERDES architectures
• Work with global teams (US, west coast and east coast), which work in different time-zones

• Candidate's background should include a minimum of 7 years of experience in CMOS SERDES or high-speed I/O IC design and development
• Working knowledge of a set of common SERDES standards and their electrical requirements
• Must have a thorough understanding of jitter and signal equalization techniques
• Proficient design experience in many of the following SERDES circuit blocks: Driver, Receiver, Serializer, Deserializer, Phase Interpolator, Low jitter PLL, High Speed Clock Distribution, Bias and Bandgap, Voltage Regulators
• Excellent problem-solving skills, analog aptitude, good communication skills and ability to work cooperatively in a team environment
• BEng, MEng or PhD

• Cadence tool experience and design experience at >10Gbps and in < 40nm technologies
• Lab test experience as part of silicon evaluation is advantageous
• Interest in publishing academic papers and presenting at conferences e.g. ISSCC, JSSC