At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Strong expertise in Verilog, HVL(SV, Specman e) with UVM/OVM/eRM methodology Experience in assertions development/closure, constraint randomization, functional and code coverages, formal verification Experiences in test-bench development
Strong RTL and GLS (w/ or w/o SDF) sim debug skills
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