Lead Design Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

The Cadence Advantage

• The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
• Cadence's employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
• The unique "One Cadence - One Team" culture promotes collaboration within and across teams to ensure customer success
• Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests
• You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other-every day.

Job responsibilities:

• 6+ years of DFT Experience with strong understanding of DFT methodologies and flows.
• Hands on Experience in ATPG, coverage analysis, ATPG DRC debug etc. Debugging DFT simulations for setup and hold corners.
• Strong understanding in fault modeling techniques and experience in architecting DFT structures for Serdes IP's
• Knowledge in test mode timing constraints
• Hands on experience with script development for automation.
• Hands on Experience in to Boundary scan in 1149.1/1149.6 & IEEE P1687 IJTAG flow.
• Exposure to Static Timing Analysis & Timing closure is required.
• Strong written and oral communication skills
• Experience working with cross functional teams

Job Role:

The candidate is expected to build Requirements for DFT for customers of the IP group and work with developing all the DFT verification and customer deliveries

To complete the scan features of the IP. Candidate is required to own the end to end development and discussion with customer for all DFT related work. Day to Day automation of script for flow development in closing the activities for DFT completion

Client-provided location(s): Bangalore, India

Job ID: Cadence-R47309

Employment Type: FULL_TIME

Posted: 2025-08-28T18:39:14