At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
This role includes the following operations and requirements:
- Work on projects to deploy Cadence RTL - GDSII tool adoption in Synthesis with Genus, Place & Route with Innovus and Static Timing Analysis with Tempus through successful design tapeouts and benchmarks
- Areas of Technology exposure include:
- RTL Synthesis/Physical Synthesis, Design constraint creation, Floorplanning, Power Grid Synthesis, Placement, Clock tree synthesis, Routing, Static timing analysis, Timing optimization, Power Analysis (Static, Dynamic, Leakage, EM)
Background / Requirements:
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- Self-starter mindset
- Excellent communication skills
- Demonstrated exposure to any of the following technical areas:
RTL Synthesis/Physical Synthesis, Design constraint creation, Floorplanning, Power Grid Synthesis, Placement, Clock tree synthesis, Routing, Static timing analysis, Timing optimization, Power Analysis (Static, Dynamic, Leakage, EM), Extraction Low power implementation.
- Must be motivated to be mentored by colleagues to increase team productivity.
- proficient software skills in the automation of physical design software including several of the following: TCL, PERL, CSH, BASH, AWK, SED, or SKILL.
- BSEE required. MSEE recommended.
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