Design Engineer II

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Location : Pune
Design Engineer II

• Experience in developing complex test bench in System Verilog using OVM/UVM methodology
• Experience in coding functional coverage and system verilog assertions.
• Experience validation of protocols such as AXI4, AHB, functionality like DMA (Direct Memory Access Controllers), Arbiters.
• Knowledge of computer architecture, AI accelerators is a big plus.
• Well versed with System Verilog and popular EDA (Cadence Xcelium preferred) simulation, System Verilog assertions and testbench methodologies
• Exposure to scripting languages like Perl, Unix shell or similar languages
• Excellent written and oral communication skills necessary

• He/She will be a part of design verification team supporting the DNA (Deep Neural Accelerator) product line.
• Work closely with the designers/micro-architect to understand the design.
• Work on complete or part of the verification plan, review the same with others in the team.
• Develop the verification infrastructure and carryout validation.
• Log/Track and validate defects.