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Cadence

Application Engineer, STA Signoff Validation

Yokohama, Japan

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Qualifications

l Knowledge of digital design fundamentals, semiconductor fundamentals, and 3+ years of experience in using and supporting STA tools; experience with EDA digital implementation tools (synthesis, P&R) and development in scripting languages such as TCL/Perl/Python a plus Good.

l Must be able to communicate in both Japanese and English.

Job Description

l This is an application engineering position responsible for pre-sales and post-sales technical support of STA sign-off tools.

l Able to learn advanced techniques for STA verification and power and performance optimization in various ASIC designs used in segments such as SOC/CPU/GPU/Network/ML.

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l Support technical evaluation/benchmarking and drive the process of implementing Cadence's digital solutions, including STA tools.

l Recognize opportunities for STA tool implementation at existing and potential customers and work with account teams to define and execute technology campaigns.

l Support STA tool implementation at existing customers (on-site and off-site) as well as customer business expansion around STA tools.

l Work closely with R&D on tool and methodology improvements to help customers grow their business.

We're doing work that matters. Help us solve what others can't.

Client-provided location(s): Yokohama, Kanagawa, Japan
Job ID: Cadence-R45332
Employment Type: Full Time