Senior Staff Semiconductor Engineer, Synth, DFx and FuSa - Returnship Program

Sr. Staff Semiconductor Engineer, Synth, DFx, FuSa

We are Aptiv - a global technology company with 190,000 specialists in 46 countries. We develop innovative software and build the hardware to bring autonomous driving cars, advanced driver-assistance systems, connected vehicles and smart cities to life in a way that only we can. We work in partnership with almost all car manufacturers. Our sensors, systems and software can already be found in almost all passenger cars today.

With our deep domain expertise, Aptiv is developing solutions that solve our customers' toughest challenges. We are enabling the transition to software-defined vehicles supported by electrified and intelligently connected architectures - which will combine to power the future of mobility.

• Perform RTL synthesis to achieve best Performance, Power, Area tradeoffs for the implemented design.
• Work on DFT and DFD implementation, including MBIST, Scan, Boundary Scan.
• Setup functional safety related implementation flows and validate design implementation.
• Setup and validate timing constraints for functional and test modes, perform static timing analysis.
• Create and verify power intent for the design, run static low power checks on gate level netlists.
• Execute and verify logic equivalence check, RTL to Gates, Gates to Gates.
• Setup signoff static timing analysis flows and achieve multi corner timing closure working with front and back end design teams.
• Run power analysis and estimate power at RTL and Gate level.
• Support Design Verification team to enable gate level SDF and UPF aware simulations.
• Interact with the design partner teams to communicate and align the implementation of SoC design.
• Innovate to improve design implementation flow through methodologies and tools.

• Bachelor's degree in electrical engineering, computer engineering, or equivalent.
• 12+ years of experience in ARM CPU-based full-chip SoC design implementation.
• Experience with ASIC synthesis, timing constraints, DFT tools.
• Experience with multi-clock design implementation, developing multi-mode flows.
• Experience with static timing analysis, equivalence checks, static low power checks
• Experience with Verilog, System Verilog, and Perl, TCL, Makefile scripting.
• Experience with power analysis using Power Artist and PTPX.
• Experience with full chip timing analysis through tapeout
• Experience and knowledge of 3rd party IP eco system.
• Experience with RTL coding for a complex silicon project from concept to launch.
• Experience in supporting SoC debug and emulator/FPGA based validation.
• Strong written and verbal communication skills.

• You can grow at Aptiv. Whether you are working towards a promotion, stepping into leadership, considering a lateral career move, or simply expanding your network - you can do it here. Aptiv provides an inclusive work environment where all individuals can grow and develop, regardless of gender, ethnicity or beliefs.
• You can have an impact. Safety is a core Aptiv value; we want a safer world for us and our children, one with: Zero fatalities, Zero injuries, Zero accidents.
• You have support. Our team is our most valuable asset. We ensure you have the resources and support you need to take care of your family and your physical and mental health with a competitive health insurance package.

• Hybrid and flexible working hours;
• Higher Education Opportunities (UDACITY, UDEMY, COURSERA are available for your continuous growth and development);
• Life and accident insurance;
• Sodexo cards for food and beverages
• Well Being Program that includes regular workshops and networking events;
• EAP Employee Assistance;
• Access to fitness clubs (T&C apply);
• Creche facility for working parents;