Summary
Posted: Apr 22, 2024
Role Number:200547994
Join our team at Apple developing complex digital IP's for Apple's custom mixed-signal integrated circuits. We have already shipped hundreds of millions of chips into Apple's existing product lines, and are developing new chips for future product lines! As a member of our mixed-signal ASIC team, you will be responsible for crafting sophisticated digital IPs for Apple power conversion and system management IC's. You will work with the system architects, product teams, verification engineers, and analog designers in creating block level specifications and implementing the designs. You will own the creation of the blocks, and take them through the concept, implementation, and validation phases, and then into mass production. Learn and use state of the art digital ASIC development flows to implement your designs. We supply silicon to Apple's industry leading hardware development teams, and collaborate closely with them. We have a close-knit, prolific team looking to add enthusiastic digital design engineers to develop new ASIC IP's. We pride ourselves for being an especially diverse team that values new approaches to deliver creativity, high productivity, and industry leading results. Join us in building Apple's next generation products. Do you want to be a part of building the "surprise and delight" in Apple's future products?
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Key Qualifications
- Experience developing digital IP's for SoC's or mixed signal IC's.
- Proven track record of delivering quality designs on schedule.
- Experience with synthesis and static timing tools.
- Expertise in Clock Domain Crossing design and verification techniques.
- Familiarity with power estimation tools and techniques.
- Familiarity with digital ASIC development flows and milestones.
- Solid understanding of low power design techniques.
Description
- Deliver complex digital IP's, meeting schedule, area, power, and performance targets. - Collaborate in developing precise design specifications for digital control blocks. - Implement physical design ready blocks in System Verilog. - Collaborate with project leads to track progress and gauge tapeout readiness. - Work with DV teams to create verification plans. - Work with silicon validation team in developing lab validation and qualification plans.
Education & Experience
Bachelor's degree and a minimum of 3 years relevant industry experience
Additional Requirements
Additional Requirements