Physical Design Engineer

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Description

APPLE INC has the following available in Austin, Texas. Perform physical design implementation of SOC (system-on-ship) blocks. Work with other teams to ensure the block integrates without issues, into the next level of the design hierarchy. Collaborate with the FE team to understand chip architecture and drive physical aspects early in the design cycle. Work with the physical design team, drive methodologies and "bestknown methods" to streamline physical design work, come up with guidelines and checklists, and track progress. Resolve design and flow issues related to physical design, identify potential solutions and drive execution. Analyze reports, query the design database for proper structure, identify issues, and write scripts using the native tool commands to develop solutions. Carry out the physical implementation of one or more complex System-On-Chip (SOC) blocks from netlist to tape-out in advanced technology nodes. Improve the current implementation methodology, tuning flows, and construction recipes to improve the power, performance, and area of implemented blocks. Work with the RTL design team to understand the logic and data flow of the block, perform placement of memories and other macros in the design, implement clock and power distribution, and placement and routing of the entire block. Optimize the design for reduced area and power and timing convergence, including understanding the clock architecture to optimize clock distribution, resolving congestion hot-spots, adding placement and grouping constraints, implementing custom routing solutions and other techniques to optimize the design. Perform various analysis tasks on the block such as Static timing analysis (STA), Voltage drop analysis static (IR)/ dynamic internal voltage deviation (IVD), Design Rule Checking (DRC)/ Layout vs. Schematic (LVS), and clean up violations to provide a clean database. Interact with top-level integration, timing, and electrical analysis teams. Participate in improving block construction recipes for a certain technology and/or tool set. Create methodology changes to improve the quality or turn-around time of implementation. Analyze collected data and utilize scripting techniques to extract trends and meaningful conclusions. Domestic Travel Required 5%. 40 hours/week.

• Master's degree or foreign equivalent in Electrical Engineering, Electronics Engineering, or related field and 5 years of experience in the job offered or related occupation.
• 5 years of experience with each of the following skills is required:
• Utilizing EDA (Electronic Design Automation) tools such as Innovus or ICCompiler, semiconductor technologies for P&R flows to produce an integrated circuit layout
• Utilizing IC validator for Physical Design Verification
• Utilizing Circuit design techniques such as clock gating and power gating to reduce power for optimizing and driving Circuit design to determine the appropriate sizes of transistors within the layout
• Perl, Shell scripting, Makefiles or TCL for design and verification
• Utilizing Pin assignment, macro placement or routing analysis to meet design specifications and address challenges such as routing congestion and optimizing wirelength
• Clock gating, power gating, or voltage scaling
• Wirelength optimization methods for Power Analysis and Optimization
• Experience with techniques to reduce dynamic power

• N/A