Physical Design Engineer

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Description

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Perform all aspects of Physical Design and implementation RTL to GDS, including initializing the floor plan, performing pin assignments, placing hard macros, and customizing critical routes. Perform Synthesis, Power, Clock Distribution, Place and Route, Timing closure, Power & Noise to make sure design specs and requirements are met. Perform Analysis and Physical and STA Verification to ensure Performance, Area, and Power are optimized at a high standard. Perform DRC and LVS to verify layout design precision. Participate in CAD Physical Design methodologies. Provide feedback on new features, customize default flow steps, and assist in flow development automation in Chip Integration to facilitate handshaking between partitions. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $143,100- $214,500/yr and your base pay will depend on your skills, qualifications, experience, and location. PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

• Master's degree or foreign equivalent in Electrical Engineering, Electronics Engineering or related field, and 1 year of experience in the job offered or related occupation.
• 1 year of experience in each of the following skills is required:
• Using Cadence or Synopsys Physical Design tool, including experience analyzing design routability.
• Experience with Synthesis and timing constraint setup.
• Experience in root-causing LVS DRC ERC issues and close PDV.
• Experience with APR flow and customization for each step.
• Understanding of CTS, experience optimizing clock skew and insertion delay.
• Experience in writing Tcl Perl Python scripts for physical design data mining and flow customization.
• Experience analyzing setup/hold violations, and experience recommending timing ECO.
• Experience in power techniques and implementing power gating.
• Collecting PPA data and understanding the tradeoff between power and performance.
• Running and analyzing EMIR and experience avoiding hot spots by construction.

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