Do you have a passion for invention and self-challenge? Do you thrive on pushing the limits of what's considered feasible. As part of a world class modem team, you'll craft sophisticated groundbreaking embedded firmware that deliver more performance in our products than ever before. You'll work across fields to transform improved hardware elements into a single, integrated design. Join us, and you'll help us innovate new cellular technologies that continually outperform the previous iterations! By collaborating with other product development groups across Apple, you'll push the industry boundaries of what wireless systems can do and improve the product experience for our customers across the world. Do you want to have an impact on every single Apple product? As a GNSS Design Verification Engineer, you will be responsible for pre-silicon RTL verification of our GNSS IP and SoC subsystem. As part of our DV team, you will develop reusable testbench and verification environment deploying the latest methodology, working closely with GNSS and SoC front-end designers and Systems Engineers.
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Description
Build block/subsystem/chip level testbench using outstanding DV methodologies. Build verification plan from specification and review with designers and systems engineers. Architect testbench with maximum reusability in mind and build UVM libraries. Generate directed and constrained random tests, debug failures, manage bug tracking, and close coverage. Create and analyze block/subsystem level coverage model and add test cases to increase coverage. Low power verification and formal verification. Improve DV flow and methodologies.
Minimum Qualifications
- Minimum requirement of a bachelors degree.
- Strong understanding of digital logic design principles.
- Knowledge of scripting (like Shell, Python, and Perl).
- Knowledge of verification techniques including problem-solving, constrained random testing, and debugging.
Preferred Qualifications
- MSEE or beyond is preferred.
- Knowledge of SOC subsystem and low power verification experience.
- Experience with SystemVerilog Assertion (SVA).
- Experience in mixed-signal modeling and simulation.
- Knowledge of digital signal process is preferred.Proficient in SystemVerilog with a deep understanding of the UVM.
Pay & Benefits
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $115,700 and $174,200, and your base pay will depend on your skills, qualifications, experience, and location.
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits.
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant .
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