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Description
APPLE INC has the following available in Irvine, California. Develop Register Transfer Level (RTL) design for the GNSS IP and SoC sub-system. Integrate microarchitecture definition and specification with architecture and system for design implementation. Conduct RTL design in SystemVerilog (SV) hardware description language. Conduct IP integration and block-level verification, and interface implementation. Perform RTL low-power design and power reduction through RTL power regression/analysis, perform RTL design quality check by running linting and cross-domain clock (CDC) checking. Work with cross-function teams (system, verification validation and firmware/software) for function, power and performance review. Check synthesis and timing sanity on the design. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $135,400 - $204,000/yr and your base pay will depend on your skills, qualifications, experience, and location. PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
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Minimum Qualifications
- Master's degree or foreign equivalent in Electrical Engineering, Computer Engineering, Electronics Engineering or related field and 2 years of experience in the job offered or related occupation.
- Experience and/or education must include:
- SystemVerilog, Verilog, and VHDL hardware description language
- Shell, Perl, or Python
- Unix, Linux OS, Perforce, or Vim
- Unified Power Format (UPF) power intent description
- Verilog Compiler Simulator (VCS)
- Digital logic design
Preferred Qualifications
- N/A
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant .
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