FE Engineer

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Description

APPLE INC has the following available in Austin, Texas. Work with the architecture team to define the design microarchitecture hierarchy and interfaces and develop microarchitecture spec. Refine the spec with reviews with other teams. Develop RTL design of one or more blocks following established design guidelines based on microarchitecture spec. Own all aspects of RTL development design. Work and collaborate with other designers in the group to deliver results. Integrate common/shared IP blocks to design and optimize memories/complex macros required for the block. Work with front-end synthesis/STA teams to ensure the timing for the block is met. Work with power/performance and functional verification team to provide high-quality blocks. Work with multi-disciplinary groups to ensure designs are delivered on time and with the highest quality by incorporating proper checks at every stage of the design process. 40 hours/week.

• Master's degree or foreign equivalent in Electrical Engineering or related field and 2 years of experience in the job offered or related occupation.
• 2 years of experience with each of the following:
• Translating SoC architecture requirements into microarchitecture specifications, including experiencec describing the blocks' functionality within the designed subsystem.
• Experience coding in Verilog/System Verilog, including designing subsystems within the System on Chip to meet power/performance and area targets
• Experience constraining and synthesizing the RTL design using synthesis tools to equivalent logic gates, and experience in timing the design using static timing analysis
• Using programming or scripting languages such as C++/Python/Perl to automate design development
• Defining verification requirements for the subsystems, including verification test-cases and ensuring the correctness of the design
• Experience in industry standard SoC interconnect protocols such as AHB/AXI, CPU architecture (ARM/RISCV) and peripherals used in SoC development
• Experience in source code management tools such as Perforce/GitHub
• Understanding gate-level netlists, including editing the netlists to make logical transformations and fixing functional bugs in the design
• Analyzing timing reports and translating this information into RTL logic changes
• Analyzing static and dynamic power consumption within the design, including designing optimizations to minimize power consumption within the subsystem

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