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Description
APPLE INC has the following available in San Diego, California. Define and develop quality assurance (QA) checks to verify exploratory data analysis (EDA) views of memory and standard cell libraries. Debug and provide solutions for digital intellectual property (IP) designers and/or users. Engage with the computer-aided design (CAD) team to implement new automation flows and QA checks. Review QA reports for memory and standard cell library releases and provide pass/fail feedback to design teams. Execute collateral generation flows for standard cell releases. Work with foundries on library releases, technical support, and model enhancement. Develop utilities to mine lib/spice data for trend or power-performance-area analysis. Automate various memory design/QA flows into an integrated flow for better efficiency and robustness. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $129,600 - $195,200/yr and your base pay will depend on your skills, qualifications, experience, and location. PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
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Minimum Qualifications
- Master's degree or foreign equivalent in Electrical Engineering or related field.
- Experience and/or education must include:
- Understanding VLSI design process in sub-micron process nodes and applying in stdcell and memory QA.
- Working with vendor and circuit designers for Virtuoso library releases, including deliver schematics, symbol, and layout.
- Using vendor tools including Cadece Liberate and Synopsys PrimeLib to characterize stdcell circuits and build timing, power, and noise models.
- Using vendor tools including Cadence ncverilog or xcelium to simulate Verilog models for stdcell and memory.
- Using formal verification tools including Cadence Conformal and Synopsys Formality to verify Verilog models for stdcell and memory.
- Developing Python scripts for daily tasks, including postprocessing and QA data.
- Developing and maintaining automation flows for stdcell and memory IPs.
- Using Matlab and Octave to analyze circuit design/simulation data for QA.
Preferred Qualifications
- N/A
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant .
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