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Description
APPLE INC has the following available in Austin, Texas. Design and develop Design-for-test solutions for SEG (Silicon Engineering Group) SOCs (system-on-chip). Implement and maintain DFT flows for SOCs. Interface with IP, design, integration, and physical design teams to implement and verify DFT design collateral and DFT functionality, as well as assisting those teams concerning DFT related items . Design and implement MBIST and Hard IP test solutions to effectively test memories and custom digital logic, at both RTL and gate netlist levels, using internal and external tools and flows. Design and implement stuck-at and at-speed Scan test solutions as required to support testing of digital logic in SOCs, including verification of said solutions. Effectively communicate with peer team and management on development activities. Contribute to common MBIST methodology development. Specific work applied to MBIST design, implementation, and verification at block and chip levels in support of SOC design, validation, and test. 40 hours/week.
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Minimum Qualifications
- Master's degree or foreign equivalent in Electrical Engineering, Computer Engineering or related field.
- Education and/or experience must include each of the following skills:
- Knowledge of fault modeling, automatic test pattern generation (ATPG) and test compression
- Utilizing Python programming language primarily for verification and checking of SCAN and MBIST
- Knowledge of Verilog, including debugging design issues
- Knowledge of Static Timing Analysis (STA), and reading STA reports
- Understanding DFT concepts and knowledge of JTAG (IEEE 1149.1, IEEE 1500), BIST, and Scan Architectures
- Simulation execution, debug of failures, creation of simulation models, and analyzing waveforms
- Knowledge of ATE Test Pattern Development, including program structure and test patterns
Preferred Qualifications
- N/A
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