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Description
APPLE INC has the following available in Austin, Texas. Verify RTL designs on an ASIC chip. Create System Verilog test benches within the UVM framework. Craft test plans and debug tests. Craft embedded C code tests. Review design and architecture specifications for next generation SOCs and IPs and work closely with design and micro-architecture teams to understand the functional & performance goals of the design. Develop test plans, coverage plans, and define methodology and test benches. Implement block/full chip environments and test cases. Run regressions, perform bug tracking, analyze code and functional coverage. Ensure deliverables align with the project goals and support cross-functional engineering teams. 40 hours/week.
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Minimum Qualifications
- Bachelor's degree or foreign equivalent in Electrical Engineering, Computer Engineering or related field.
- Experience and/or education with each of the following:
- Knowledge of one of the scripting languages (Python, Perl, TCL) to post-process the regression logs and analyze the failure.
- Verification methodologies and simulator tools to build and run the test cases to validate complex SOC's IP and subsystem blocks.
- Knowledge of waveform viewer to enable the debugging of failed test cases and uncover the bugs in the design.
- Knowledge of CPU architecture and understanding of complex SOC's architecture to define the complex test scenarios.
- Object-oriented programming (OOP) to create the transaction-level reusable testbenches for IP and subsystem blocks inside the SOCs.
- Knowledge of coverage collection and analysis and coverage data to ensure the scalable test benches exercise the features and codebase.
Preferred Qualifications
- N/A
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